1. Field of the Invention
This invention relates to gate arrays, and more particularly to a field programmable gate array that is programmed by loading a bitstream of data.
2. Description of the Background Art
Digital logic can be implemented using several options: discrete logic devices, often called small-scale integrated circuits or SSI, programmable devices such as programmable logic arrays (PLAs) or programmable logic devices (PLDs), masked-programmed gate arrays or cell-based application specific integrated circuits (ASICs), and field programmable gate arrays (FPGAs).
FPGAs are general purpose programmable devices that are customized by the end users. FPGAs are composed of an array of configurable logic blocks that are programmably interconnected. The basic device architecture of an FPGA consists of an array of configurable logic blocks (CLBs) embedded in a configurable interconnect structure and surrounded by configurable I/O blocks (IOBs). An IOB allows signals to be driven off-chip or optionally brought onto the FPGA onto interconnect segments. The IOB can typically perform other functions, such as tri-stating outputs and registering incoming or out-going signals. The configurable interconnect structure allows users to implement multi-level logic designs (multi-level refers to logic in which the output signal of one logic unit provides input to another logic unit and the output of that provides input to another, etc.). An FPGA can support tens of thousands of gates of logic operating at system speeds of tens of megahertz. The FPGA is programmed by loading programming data into the memory cells controlling the configurable logic blocks, I/O blocks, and interconnect structure. Further information about FPGAs appears in "The Programmable Logic Data Book", copyright 1994 by Xilinx, Inc. and available from Xilinx, Inc. at 2100 Logic Drive, San Jose, Calif. 95124, which is incorporated herein by reference.
Each configurable logic block in the FPGA can include configuration memory cells for controlling the function performed by that logic block. These configuration memory cells can implement a lookup table, control multiplexers, and control other logic elements such as XOR gates and AND gates. A lookup table stores a truth table which implements that combinational logic function corresponding to the truth table. Each configurable logic block may also be defined to include an adjacent portion of the interconnect structure. The interconnect structure includes programmable interconnect points which control the connection of wiring segments in the programmable interconnect network of the FPGA. Each programmable interconnect point may be a pass transistor controlled by a configuration memory cell. Wire segments on each side of the pass transistor are either connected or not connected depending on whether the transistor is turned on by the corresponding configuration memory cell. The multiplexer is a special-case one-directional routing structure that is controlled by a configuration memory cell. Although the multiplexer can be any width, controlling multiplexers with many inputs will require additional configuration memory cells. Switches that are built using multiplexers require fewer configuration memory cells than the number of multiplexer inputs.
Configuration is the process of loading a bitstream containing the program data into the configuration memory cells which control the configurable logic blocks and I/O blocks of the FPGA. The bitstream is loaded into the FPGA serially to minimize the number of pins required for configuration and to reduce the complexity of the interface to external memory. The bitstream is broken into packets of data called frames. As each frame is received, it is shifted through a frame register until the frame register is filled. The data in the frame register of the FPGA are then loaded in parallel into one row of configuration memory cells forming the memory array. (The configuration memory cells which control a configurable logic block typically occupy a two dimensional section of the array.) The configuration memory cells make up the lookup tables and control programmable interconnect points, multiplexers, and other programmable elements of a configurable logic block or I/O block. Following the loading of the first frame, subsequent frames of bitstream data are shifted into the FPGA, and another row of configuration memory cells in the array of CLBs is designated to be loaded with a frame of bitstream data.
As an FPGA product line goes through its product life cycle, added features and upgrades of the original product versions are often made. In most cases, the original FPGA version does not anticipate in advance all the features that will be added in the upgrades. The upgraded FPGAs typically expand on the previous FPGA versions by the addition of minor variations. For example, an upgraded FPGA may have user writeable memory where the original version does not, or a later FPGA has carry logic and the original FPGA does not have carry logic. These variations between FPGA versions can require using extra bits in the configuration memory to program the added features. As additional bit locations in the configuration memory cells are required, one practice is to expand the frame register to accommodate the additional bit locations. However, the expanded frame register version of the FPGA is no longer bitstream compatible with the original version. Different sized bitstreams are used to program the original version and the expanded version of the FPGA. Maintaining bitstream compatibility as an FPGA product line goes through its product life cycle is important. It is desirable that a newly upgraded FPGA still be able to accept the previous FPGA bitstream so that a user need not generate a new bitstream in order to use an upgraded FPGA.
Also, it may be advantageous to a producer of FPGAs to stop producing earlier versions of the FPGA product line and just produce the later versions of the FPGA product line. By preserving bitstream compatibility throughout an FPGA product life cycle, later versions of the FPGA product line can be used to replace the earlier versions so that producers of FPGAs can reduce the number of different FPGAs in their inventory and yet customers need not redesign their bitstreams.
In the past, Xilinx, Inc has sold FPGAs which initially were configured by bitstreams having bits which did not get loaded into memory cells in a configuration memory. These unused bits were provided in order to fill out a rectangular array of bits for specified parts of the FPGA, such as a logic block of the FPGA. In these FPGAs, the unused bits were loaded from the bitstream into a frame register but were not loaded into a portion of the memory which configured the FPGA. The software which generated bitstreams for these first FPGAs always selected a default value for the unused bits. When designing second generation FPGAs, Xilinx, Inc. was able to add features while maintaining compatibility with older bitstreams. Since the unused bits in the earlier bitstreams were always given a default value, the new FPGAs were designed to perform identically to the older FPGAs when the unused bits carried their default values. But when the previously unused bits Carried the opposite value, additional features not available in the older FPGAs were implemented. Thus the user could load an older bitstream into a newer FPGA and get the same result obtained in the older FPGA or by generating a new bitstream using the previously unused bits the user could control the new features. In the second generation FPGAs, additional memory cells were provided in the configuration memory and these additional memory cells were then controlled by the previously unused bits. However, in these earlier FPGAs, no planning was done to allow for future expansion of bitstreams so that future FPGAs can be designed which are bitstream compatible with earlier FPGAs but can be programmed to provide additional features.
Therefore, it is desirable to design FPGAs that can incorporate added new features and upgrades while maintaining bitstream compatibility. The improved FPGA should be capable of meeting the expansion requirements as the FPGA product line goes through its product life cycle.